The ongoing focus on miniaturization and the increasing complexity and speed requirements of integrated circuits demand continuously higher density integration. To achieve this, there is an ongoing downscaling in the dimensions of the active devices, as well as of the structures interconnecting these devices. These interconnect structures can comprise multiple metal levels which are, depending on the desired interconnect pattern, either separated from one another by means of interlevel insulating layers or connected to one another by means of a conductive connection through the insulating layer. Besides this downscaling of the dimensions, additional measures are required to be able to meet the stringent speed specifications. Conventionally, the metal levels are aluminum (Al) layers while the insulating layers are oxide layers. In order to reduce the signal delay, one can choose a metal layer with a higher conductivity compared to aluminum and/or choose insulating layers with a lower dielectric constant compared to oxide layers. To meet these objectives copper-containing metal layers and/or copper-containing connections will be introduced in the near future.
The use of copper (Cu) in interconnect structures has some commonly known disadvantages. Cu can have a high diffusion in the surrounding insulating layers, which negatively affects the reliability and the signal delay. Several solutions have been proposed to solve this problem. Materials such as refractory metals have been used as a barrier layer to prevent copper from migrating into the surrounding layers.
The currently used technique inhibits the migration of copper ions in the surrounding layers by depositing a barrier layer in a non-selective way. FIG. 1 illustrates the resulting structure. The conductive bottom surfaces 10 as well as the insulating sidewalls 12 (which include the trench floors 13) of the opening in an insulating layer 14 are covered with a barrier material 16. In case of chemical vapor deposition (CVD), the barrier 16 is conformally deposited. In case of physical vapor deposition (PVD), the coverage of the vertical walls and the bottom of the opening is thinner compared to the coverage of the top of the structure. However, the ratio between vertical and horizontal coverage can be tuned to a certain extent by modifying the process parameters like deposition power, the bias of deposition, etc.
Several problems are related to the deposition of barrier layers. Since the barrier layer is deposited on both the insulating sidewalls 12 and the conductive bottom wall 10 of an opening in an insulating layer 14, 15, the occurrence of a barrier layer on the bottom wall 12 causes several inconveniences. When the opening is filled with a metal 18, the barrier layer 16 between the overlying metal 18 and the underlying metal 20 has a detrimental effect on the electromigration behavior of the structure, since the barrier 16 serves as a flux divergence point for the electrons. Consequently, a discontinuity for the metal atoms occurs with electromigration during subsequent circuit operation.
The presence of the barrier layer 16 on the bottom surface 10 of an opening in an insulating layer creates additional inconveniences. Since the adhesion between the barrier layer 16 and the underlying conductive layer 20 is not always good, the current flowing between the different conductive levels will be influenced, having a negative impact on the reliability and the resistivity of the conductive path.
In U.S. Pat. No. 5,904,565, a direct copper-to-copper connection between different levels in an integrated circuit is disclosed. In a first step, a barrier layer is conformally deposited into the via. In a second step, the barrier layer covering the lower copper level is selectively removed by anisotropically etching. The barrier covering the vertical sidewalls remains. This method implies a more complex process with more process steps than conventional barrier formation, which causes additional difficulties by implementation. Furthermore, the cost will increase.
Consequently, a need exists for a method of forming a direct metal-to-metal contact by selectively depositing a barrier layer on the insulating surfaces of an opening formed in an insulating layer, such that superior conductive behavior of the metal levels in an integrated circuit (IC) can be obtained.